
===================
FPGA Link
===================

.. warning::

   The reference design and the on-the-wire format are not stable and will be
   subject to incompatible changes with further development.

The FPGA link output of the |ttx-name| allows you to connect an FPGA of your
own design to the |ttx-name| via an Ethernet-based protocol and benefit from
higher data throughput and lower latency compared to USB.

In a typical use case, you want to use either process tags at a higher rate than
the USB connection to the PC allows or integrate the measurements into a test
fixture and trigger events based on the measurements.

The SFP+ port on the |ttx-name| can be used either with a DAC or
fiber transceivers to connect to your own FPGA. We recommend using the
`OpalKelly XEM8320 <https://www.opalkelly.com/products/fpga-integration/xem8320>`_ for your custom
design.

The QSFP+ port on the |ttx-name| should be used with a fiber transceiver to connect to your own FPGA.
We also recommend using the `OpalKelly XEM8320
<https://www.opalkelly.com/products/fpga-integration/xem8320>`_ together with the `SZG-QSFP
<https://www.opalkelly.com/products/syzygy/szg-qsfp>`_ for your custom design.

.. note::

   We recommend using the SFP+ port unless the higher bandwidth is necessary.

.. warning::

   There is currently no retransmission support so if corruption occurs during
   transmission, tags will be permanently lost. Please verify that your data
   link is of high quality or that tag loss can be tolerated.

Getting Started with SFP+
-------------------------

To enable the FPGA link output of the Time Tagger use :cpp:func:`~TimeTagger::enableFpgaLink`. Start by
enabling the FPGA link on channel 1:

::

   from Swabian import TimeTagger
   tagger = TimeTagger.createTimeTagger()
   tagger.enableFpgaLink([1], "", TimeTagger.FpgaLinkInterface.SFPP_10GE)

To receive the tags, use our `Time Tagger FPGA link reference
<https://github.com/swabianinstruments/TimeTagger-FPGALink-Reference/>`_ design.
Follow the instructions in the `XEM8320 README
<https://github.com/swabianinstruments/TimeTagger-FPGALink-Reference/blob/main/target/opalkelly-xem8320/README.md>`_
to build the reference design. Connect the SFP+ port on the |ttx-name| to the
``SFP 1`` port on the XEM8320 and load the bitstream on the XEM8320. You should now
be able to observe the LED ``D1`` on the XEM8320 matching the input state on channel
1 of the |ttx-name|.

To verify the link quality, activate a test signal as follows:

::

    tagger.setTestSignal([1], True)

and reload the bitstream on the XEM8320. LED ``D6`` should stay dark, indicating
that the channel 1 events are arriving at the expected time without drops.

Using QSFP+
-----------

QSFP+ is quite similar to using SFP+. Start by enabling the FPGA link for the QSFP+ interface for input channel 1 of the |ttx-name|:

::

   from Swabian import TimeTagger
   tagger = TimeTagger.createTimeTagger()
   tagger.enableFpgaLink([1], "", TimeTagger.FpgaLinkInterface.QSFPP_40GE)

Similarly use our `Time Tagger FPGA link reference
<https://github.com/swabianinstruments/TimeTagger-FPGALink-Reference/>`_ design, but follow the instructions in the `README
<https://github.com/swabianinstruments/TimeTagger-FPGALink-Reference/tree/main/target/opalkelly-xem8320-qsfp>`_ for the QSFP+ interface.

Connect the QSFP+ port of the |ttx-name| with the ``SZG-QSFP`` module which has to be connected to Port E of the XEM8320. You should now
be able to observe the LED ``D1`` on the XEM8320 matching the input state on channel
1 of the |ttx-name|.

.. note::

   Using the reference design with QSFP+ requires the Xilinx `EF-DI-LAUI-SITE` IP core license. We recommend starting with the SFP+ connection.

.. warning::

   Only one output is active at the same time. Enabling the QSFP+ port disables the SFP+ port and vice-versa.

Modifying the reference design
------------------------------
Follow the instructions in `Building you own design
<https://github.com/swabianinstruments/TimeTagger-FPGALink-Reference/blob/main/target/opalkelly-xem8320/README.md#user-content-building-your-own-design>`_.
