Hardware

Output Channels

The Pulse Streamer 8/2 has 8 digital and 2 analog output channels. The electrical characteristics are tabulated below.

Digital Output

Hardware Version 3.xHardware Version <= 2.x

Property	Value
Output into 50 Ω	0 and 2.6 V
Output impedance [1]	~ 13 Ω
Sampling rate	1 GHz
Rise/fall time (20%-80%)	< 300 ps
Minimum pulse width	2 ns
TIE Jitter, Typical (HPF 12 kHz) [2]
RMS jitter	60 ps
Peak jitter	< 350 ps
TIE Peak Jitter, Worst Case (HPF 12 kHz) [3]
Single channel	< 350 ps
All channels active	< 450 ps

[2]

Measurement of time interval error on like edges with a 12 kHz highpass filter, excluding duty cycle distortion (DCD). 600 K events were conducted using independent random pulses across all channels. Pulse durations were distributed between 4 ns and 2 µs according to a log-uniform distribution. The value slightly varies with the number of active channels and the data rate on the target channel.

[3]

Worst case of bandwidth-limited time interval error (HPF 12 kHz) over periodic and non-periodic patterns with 600 K events on the target channel with periodic interfering patterns on adjacent channels. Not all pattern/interference combinations have been exhaustively tested.

RMS and Peak Jitter Specification

The RMS value is the standard deviation of the measured jitter distribution. For 600 k events, a purely Gaussian distribution, which contains random jitter (RJ) only, would yield a peak jitter of ~5 × RMS (, where is the estimated peak jitter, the standard deviation (RMS jitter), and the number of events). In the typical case, jitter is RJ-dominated with a small deterministic contribution, resulting in an empirically observed peak jitter of ~6 × RMS.

In the worst case (all channels active), deterministic jitter (DJ) – e.g. from inter-channel crosstalk or power supply noise – gains significant weight, breaking the 6 × RMS relationship. A peak jitter derived from the worst-case RMS would substantially overestimate the actual peak excursion. Therefore, only the peak value is specified for the worst case.

The worst-case peak jitter specification covers the following conditions (not all signal patterns, pulse widths, and frequency combinations have been exhaustively tested):

• Periodic interference: Periodic signals on the target channel combined with periodic interference signals on adjacent channels (particularly T = 16 ns / f = 62.5 MHz on the adjacent channels).

• High-density pulse patterns: Patterns containing the minimum pulse width of 2 ns, or independent high-density pulse sequences (avg. pulse width < 10 ns) on all channels concurrently.

Minimum pulse width: The worst-case jitter specification may be exceeded if 2 ns low pulses adjacent to longer high pulses occur at high repetition rates within the pattern.

Clock Coupling: An external clock introduces device-dependent jitter, particularly on Digital Channel 2. The exact values depend on the external clock source.

For application-specific jitter questions or to receive the latest characterization data, please contact our support team.

Note

Since Q2 2026, jitter specifications have been based on high-pass filtered TIE measurements (12 kHz corner). Both the specified values and the set of parameters differ from earlier revisions of this document.

Analog Output

Hardware Version 3.xHardware Version 3.1/3.0Hardware Version <= 2.x

Property	Value
Sampling rate	125 MHz
Output into 50 Ω	-1.0 to 1.0 V
Output impedance [1]	~ 2 Ω
Bandwidth (-3db)	50 MHz
Resolution	14 bit
Offset error (into 50 Ω load)	< 2 mV
Gain error (into 50 Ω load)	< 1 %
Rise/fall time (20%-80%)	< 7 ns
Step response overshoot (typ.)	25 %
Output settling time (1%)	< 100 ns
Crosstalk (analog)	< -45 dB
Crosstalk (digital)	< -55 dB

Note

[1] (1,2,3,4,5)

The Pulse Streamer 8/2 expects a 50 Ω termination to avoid reflections. All output voltages assume the 50 Ω load termination. Without a termination, you will get a slightly higher output voltages due to the output impedance being greater than 0 Ω.

Trigger Input

The Pulse Streamer 8/2 has one external trigger input, which can be enabled by software. By default, the Pulse Streamer 8/2 is automatically rearmed after a sequence with a finite number of n_runs has finished. The sequence can be retriggered after the sequence has finished and the retrigger dead-time has passed. Triggers that arrive too early are discarded. Information about how to configure the trigger functionality of the Pulse Streamer 8/2 can be found in the Running pulse sequences section

Electrical characteristics:

Hardware Version 3.4Hardware Version <= 3.3Hardware Version 2.x

Property	Value
Termination	50 Ω
Max. voltage range (no damage)	-0.3 to 5.3 V
Input voltage range	0 to 5 V
Trigger level	0.5 V
Minimum pulse width (rising/falling) [6]	4/5 ns
TriggerToData (rising/falling, typ.) [6]	100/101 ns
TriggerToData jitter	±0.5 ns
Retrigger dead-time [8]	< 50 ns

[6] (1,2)

Measured with a trigger signal amplitude of 0 to 2.6 V

[8] (1,2,3)

The minimum time gap required between the end of the streamed sequence to trigger the next sequence.

TriggerToData

The trigger-to-data delay depends on the phase of the incoming trigger event relative to the clock of the Pulse Streamer 8/2 running at 125 MHz. In the default case (internal clock signal), the trigger-to-data signal path exhibits a delay that is uniformly distributed over 1 ns around 100 ns (typically).

TriggerToData: Trigger signal (bottom - delayed by ~92ns) and the data-out signal (top)

This distribution occurs because the trigger signal is sampled at double the data rate of the fastest available clock signal (500MHz).

How to further reduce the TriggerToData jitter

One way to further reduce the TriggerToData jitter is to use the Pulse Streamer 8/2 as a master device, assuming that the other devices have a lower TriggerToData jitter.

Another possibility is to phase-align the Pulse Streamer 8/2 clock and the trigger signals.

Synchronization of Trigger and Pulse Streamer 8/2 clock

The jitter of the TriggerToData can be avoided by phase aligning the trigger signal with the Pulse Streamer 8/2 clock. You can achieve synchronization by using the external 125 MHz or 10 MHz clock input capability of the Pulse Streamer 8/2 (see Using an external clock). All internal clocks related to the Pulse Streamer 8/2 output stages will be derived from the signal fed to the clock input.

If the external trigger and the clock of the Pulse Streamer 8/2 are phase-aligned, it will lead to a fixed TriggerToData with a jitter of ~100 ps. The exact value of TriggerToData depends on the trigger’s phase position relative to the positive edge of the clock signal, as shown in the following figure:

Pulse Streamer 8/2 clock (top, 125MHz), trigger signal (bottom left) and the data-out signal range (bottom center)

External Clock Input

The Pulse Streamer 8/2 has one input that can receive an external 125 MHz or 10 MHz reference clock. Further information about how to set the clock source of the Pulse Streamer can be found in the Using an external clock section.

Electrical characteristics:

Hardware Version 3.xHardware Version 2.xHardware Version <= 2.1

Property	Value
Termination	50 Ω
Coupling	AC coupled
Amplitude range	0.2 - 5 Vpp
Accepted frequencies	10 or 125 MHz

LEDs

The Pulse Streamer 8/2 has two LEDs that provide information about the status of the device and the network connection.

Device status LED:

green	Pulse Streamer successfully booted
blinking green/orange	sequence is streaming
orange	waiting for trigger/retrigger
blue	sequence finished - retrigger disabled
blinking yellow/white (slow)	wait in idle state
blinking green/white	wait while repeating
blinking red/white	expected data did not arrive in time
purple	breakpoint - waiting for trigger
blinking purple/blue	breakpoint - trigger not armed
blinking blue	no valid license
continuous red	general error

Network LED:

red	no configuration/connection
blinking green/red	setting DHCP - no connection
green	setting DHCP - connection found
yellow	setting DHCP - connection found via Auto IP
blinking blue/red	setting static IP - no connection
blue	setting static IP - connection found