Hardware
Output Channels
The Pulse Streamer 8/2 has 8 digital and 2 analog output channels. The electrical characteristics are tabulated below.
Digital Output
Property |
Value |
---|---|
Output into 50 Ω |
0 and 2.6 V |
Output impedance [1] |
~ 13 Ω |
Sampling rate |
1 GHz |
Rise/fall time (20%-80%) |
< 300 ps |
Minimum pulse width |
2 ns |
RMS jitter |
< 50 ps |
Property |
Value |
---|---|
Output into 50 Ω |
0 and 3 V |
Output impedance [1] |
~ 5 Ω |
Sampling rate |
1 GHz |
Rise/fall time (20%-80%) |
< 1.1 ns |
Minimum pulse width |
3 ns |
RMS jitter |
< 50 ps |
Analog Output
Property |
Value |
---|---|
Sampling rate |
125 MHz |
Output into 50 Ω |
-1.0 to 1.0 V |
Output impedance [1] |
~ 2 Ω |
Bandwidth (-3db) |
50 MHz |
Resolution |
14 bit |
Offset error (into 50 Ohm load) |
< 2 mV |
Gain error (into 50 Ohm load) |
< 1 % |
Rise/fall time (20%-80%) |
< 7 ns |
Step response overshoot (typ.) |
25 % |
Output settling time (1%) |
< 100 ns |
Crosstalk (analog) |
< -45 dB |
Crosstalk (digital) |
< -55 dB |
Property |
Value |
---|---|
Sampling rate |
125 MHz |
Output into 50 Ω |
-1.0 to 1.0 V |
Output impedance [1] |
~ 2 Ω |
Bandwidth (-3db) |
50 MHz |
Resolution |
14 bit |
Offset error (into 50 Ohm load) |
< 2 mV |
Gain error (into 50 Ohm load) |
< 1 % |
Rise/fall time (20%-80%) |
< 7 ns |
Step response overshoot (typ.) |
25 % |
Output settling time (1%) |
< 100 ns |
Crosstalk (analog) |
< -45 dB |
Crosstalk (digital) |
< -55 dB |
Warning
Around 20s after power-cycling, the analog outputs have a short pulse (duration ~30ns) with a voltage level of -0.5V.
Property |
Value |
---|---|
Sampling rate |
125 MHz |
Output into 50 Ω [2] |
-1.0 to 1.0 V |
Output impedance [1] |
~ 2 Ω |
Bandwidth (-3db) |
50 MHz |
Resolution |
14 bit |
Accuracy [3] |
±5 mV |
Rise/fall time (20%-80%) |
< 7 ns |
Crosstalk (analog) |
< -45 dB |
Crosstalk (digital) |
< -55 dB |
Note
Warning
During power-up, the analog outputs have an undefined output voltage value in the range of -1V to 1V.
Trigger Input
The Pulse Streamer 8/2 has one external trigger input, which can be enabled by software. By default, the Pulse Streamer is automatically rearmed after a sequence with a finite number of n_runs has finished. The sequence can be retriggered after the sequence has finished and the retrigger dead-time has passed. Triggers that come early are discarded. Information about how to configure the trigger functionality of the Pulse Streamer can be found in the Running pulse sequences section
Electrical characteristics:
Property |
Value |
---|---|
Termination |
50 Ω |
Max. voltage range (no damage) |
-0.3 to 5.3 V |
Input voltage range |
0 to 5 V |
Trigger level |
0.5 V |
Minimum pulse width (rising/falling) [4] |
4 ns |
TriggerToData (rising/falling, typ.) [4] |
65/66 ns |
TriggerToData jitter |
±4 ns |
Retrigger dead-time [6] |
< 50 ns |
Property |
Value |
---|---|
Termination |
50 Ω |
Max. voltage range (no damage) |
-0.3 to 5.3 V |
Input voltage range |
0 to 5 V |
Trigger level |
0.5 V |
Minimum pulse width (rising/falling) [5] |
4/8 ns |
TriggerToData (rising/falling, typ.) [5] |
65/68 ns |
TriggerToData jitter |
±4 ns |
Retrigger dead-time [6] |
< 50 ns |
Property |
Value |
---|---|
Termination |
50 Ω |
Max. voltage range (no damage) |
0 to 3.3 V |
Input voltage range |
0 to 3.3 V |
Low-level range |
0 to 0.8 V |
High-level range |
2.0 to 3.3 V |
Minimum pulse width |
< 2 ns |
TriggerToData (typ.) |
60 ns |
TriggerToData jitter |
±4 ns |
Retrigger dead-time [6] |
< 50 ns |
Note
The minimum time gap required between the end of the streamed sequence to trigger the next sequence.
TriggerToData
The trigger to data delay depends on the phase of the incoming trigger event relative to the clock of the Pulse Streamer (125 MHz). The trigger to data signal path shows for the default case (internal clock signal) a delay that is equally distributed between 61 and 69 ns as shown in the following figure.
The reason for this distribution is that all output clocks are derived from the Pulse Streamer clock signal (125 MHz). The positive clock edge samples the trigger events which results in an accuracy of 8 ns. This situation is visualized in the following figure.
How to avoid the trigger to data jitter
One way to circumvent the TriggerToData jitter is to use the Pulse Streamer as a master device. When the other devices have a lower TriggerToData jitter, this can solve the issue.
Another possibility is to phase-align the the Pulse Streamer clock and the trigger signal.
Synchronization of Trigger and Pulse Streamer clock
The jitter of the TriggerToData can be avoided by phase aligning the trigger signal with the Pulse Streamer clock. You can achieve synchronization by using the external 125 MHz clock input capability of the Pulse Streamer 8/2 (see Using an external clock). All internal clocks related to the Pulse Streamer output stages will be derived from the signal fed to the clock input.
If the external trigger and the clock of the Pulse Streamer 8/2 are phase-aligned, it will lead to a fixed TriggerToData value between 61-69 ns. The exact value depends on the trigger’s phase position and the positive edge of the clock signal as shown in the following figure:
Note
When the trigger is exactly at the position of the sampling clock, the TriggerToData of each trigger will be randomly +0ns or +8ns as illustrated in the figure below:
When this situation occurs, please shift your signal ideally by half the clock period (4ns), e.g., with a longer or shorter cable on the clock or trigger signal line.
Note
In case you are using 10MHz as an external reference clock for the Pulse Streamer, phase alignment with the 125 MHz is not possible.
External Clock Input
The Pulse Streamer 8/2 has one input that can receive an external 125MHz or 10 MHz reference clock. Further information about how to set the clock source of the Pulse Streamer can be found in the Using an external clock section.
Electrical characteristics:
Property |
Value |
---|---|
Termination |
50 Ω |
Coupling |
AC coupled |
Amplitude range |
0.2 - 5 Vpp |
Accepted frequencies |
10 or 125 MHz |
Property |
Value |
---|---|
Termination |
50 Ω |
Input voltage range |
0 to 3.3 V |
Low-level range |
0 to 0.8 V |
High-level range |
2.0 to 3.3 V |
Accepted frequencies |
10 or 125 MHz |
Warning
Due to hardware limitations, there is a 100mV ripple on the digital outputs if an external clock source is connected to the Pulse Streamer 8/2. The analog channels are not affected.
Property |
Value |
---|---|
Termination |
50 Ω |
Input voltage range |
0 to 3.3 V |
Low-level range |
0 to 0.8 V |
High-level range |
2.0 to 3.3 V |
Accepted frequencies |
10 or 125 MHz |
Warning
Due to hardware limitations, there is a 100mV ripple on the digital outputs if an external clock source is connected to the Pulse Streamer 8/2. The analog channels are not affected.
Note
These hardware revisions of the Pulse Streamer 8/2 have ambiguous input port labels. The correct input port for the external clock is the second one on the left side labeled with *GP In* or *SlowDigital 1*.
Status LEDs
The Pulse Streamer 8/2 has two LEDs showing information about the status of the device and the network connection.
Device status LED:
green |
Pulse Streamer successfully booted |
blinking green-orange |
sequence is streaming |
orange |
waiting for trigger/retrigger |
blue |
sequence finished - retrigger disable |
blinking blue |
no valid license |
continuous red |
error |
Network LED:
red |
no configuration/connection |
blinking green-red |
setting DHCP - no connection |
green |
setting DHCP - connection found |
blinking blue-red |
setting static IP - no connection |
blue |
setting static IP - connection found |