Using an External Clock with Time Tagger

Using an external clock with Swabian Instruments’ Time Taggers can enhance the precision and stability of time measurements beyond that achieved with the internal clock stability of the device. Leveraging an external clock is particularly important in applications requiring synchronization with other equipment or across different systems, such as remote Time Taggers . There are two main options for integrating an external clock: by utilizing the standard external clock input “CLK input” and using an input channel and leveraging our patented software clock functionality (preferred method):

  1. The standard CLK input allows for a direct connection to an external hardware clock with frequencies of either 10MHz or 500MHz. This provides a straightforward method for synchronizing the Time Tagger with an external timing source. The primary advantages of this approach are its minimal latency due to the direct hardware connection and the fact that it does not consume USB bandwidth, as the clock signal is not transmitted to the PC, unlike the software clock approach. Additionally, it is important to note that an external clock can only be connected to the CLK input in the Time Tagger Ultra and Time Tagger X models, as this functionality is not available in the Time Tagger 20.

  2. The software clock provides an innovative method for integrating an external clock without the need for dedicated hardware. Enabling the software clock on a given input channel initiates a software Phase-Locked Loop (PLL). This software PLL utilizes a periodic input signal applied to one input channel as the reference clock signal for rescaling timestamps in the data stream from the other input channels. The PLL provides a new time base with “ideal clock tags” separated by exactly the defined clock period. The software clock continuously processes the timestamp data stream via a robust averaging calculation managed by a control loop mechanism, replacing timestamps from a specific input channel with more accurate timestamps in real time. These averaging and rescaling calculations are performed on-the-fly, maintaining a low latency typically below one second, which is crucial for immediate data processing and display. Additional information can be found in the documentation and the related Patent .

The advantages of using SoftwareClock for reference signal or external clock

When choosing the standard CLK approach, it is crucial that the 10MHz or 500MHz reference clock be uncorrelated with the signals under investigation. Particularly in situations when the reference clock signal is correlated with the signals to be measured or analyzed, the Software Clock is highly recommended. See below for further explanation [*].

Two key advantages of the Software Clock are the increased versatility and reduced input jitter:

  • SoftwareClock allows for a broad input frequency range not limited to 10 MHz or 500 MHz and calculates phase error estimators. Acceptable input frequencies range between 1 kHz and 475 MHz or 700 MHz depending on whether one is using the Time Tagger Ultra or Time Tagger X, respectively. Depending on the clock frequency, an event divider might be needed to save the USB bandwidth. This functionality is particularly useful in production or QC environments where a large amount of oscillators may need to be characterized, e.g. leveraging our FrequencyStabilityAnalysis or FrequencyCounter measurement functions.
  • For applications in which high time resolution is critical, one can average out the input jitter in which the clock channel is input. This is accomplished by considering several earlier or later timestamps that occurred at known multiples of a clock period, leading to a lower jitter for measurements including the clock channel directly, thus resulting in improved Instrument Response Function.

[*] The picosecond timing resolution of our Time Taggers relying on a Time-to-Digital Converter (TDC) implemented in a Field Programmable Gate Array (FPGA) is obtained through a time interpolation technique, known as the Tapped Delay Line (TDL) method. The TDL consists of a series of amplifiers through which the signal propagates. The fine time measurement is determined by the depth of signal propagation into the delay chain within a clock cycle. Each element in the chain has a specific delay, and accurate timing requires knowledge of these individual delays, calculated as their cumulative sum. However, these delays are sensitive to temperature variations, necessitating continuous calibration to ensure precision. The Time Tagger automatically performs continuous calibration on the fly by assuming uncorrelated signals.

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